1. Field of the Invention
This invention relates in general to a device for reassembling ATM cells, and more particularly to an ATM reassembly controller that optimizes the utilization of host memory space and hardware resources such as I/O bus bandwidth, host memory bandwidth, memory system bandwidth and CPU resources.
2. Description of Related Art
ATM stands for "Asynchronous Transfer Mode". ATM has been chosen as a transport technology for the B-ISDN (Broadband Integrated Services Digital Network) protocol stack. The ATM technology is cell based and ATM networks are connection oriented. In addition, the connections are virtual and the connection identifiers do not have a global significance when compared to other networking technologies such as ethernet, token-ring, etc.
ATM networks are provisioned much the same as frame relay networks. Subscribers select access and port speeds and a sustained information rate (SIR), which is comparable to frame relay's committed information rate (CIR). For example, subscriber traffic can enter a carrier's ATM network at 45 Mbit/s with an SIR of 10 Mbit/s. The traffic is guaranteed to travel through the network at 10 Mbit/s but can burst to higher bit rates when network capacity is available.
Because ATM is ideal for switch cost and the fact that it is designed to carry voice, data and video, ATM is quickly becoming the favored Local Area Network (LAN) technology. As a result, many companies are now shipping ATM switches that are ATM based and provide translations to other LAN technologies such as Ethernet, Token ring, and T1. Further, ATM networks are already replacing most other WANs, MANs and LANs. It is also a minor addition to include the regular office telephone communications function in an ATM based link to the office.
One of the key features of ATM is that it spans the local and wide area. The technology begins with voice, data, and video, and then slices and dices them into 53-byte cells. The 53-byte cells are then transmitted over high-speed circuits. Intelligent end equipment takes care of segmentation and reassembly (SAR).
ATM cell reassembly refers to the reception of multiple 53 byte ATM cells, extraction of the payload which is normally 48 bytes, and combining the payloads of multiple cells to reconstruct the Protocol Data Unit (PDU) that was transmitted from the source. Typically, ATM cells received in a sample period are from many different virtual channels. Thus, the ATM reassembly controller must be able to reassemble PDUs for multiple channels in parallel. After completing the transfer of the entire PDU, the reassembly controller must report the event to the host CPU along with appropriate PDU descriptors.
The ATM PDU can be any size from 1 to 65,535 bytes. For the AAL-5 format, the reassembly controller does not know the size of the PDU until the last cell is received which has the Payload Type Indicator (PTI) bits set to indicate that the cell is the last cell of a PDU. Typical memory buffers are usually 4096 bytes in size.
Since ATM reassembly may involve thousands of small PDUs in a short period of time, previous reassembly controller designs employ the definition of a smaller memory buffer size, such as 128 bytes. The reassembly would begin by writing 48 byte payloads to a small buffer. The small buffer would overflow if the PDU was sufficiently large. In this situation, the reassembly controller would continue by starting to fill a large buffer. However, the PDU sizes vary and there is frequently unused areas of small and large buffers.
Furthermore, the efficient use of the I/O bus, host memory bus, memory system resources and CPU resources is another area of concern. The ATM cell payloads of 48 bytes are too small to efficiently transfer to host memory. The status information for the PDU is even smaller. Pointers to the buffers where the data is stored must also be conveyed to the application and these pointers are typically less than 48 bytes. Such small transfers needlessly tie-up the bus and host resources.
Thus, it can be seen that there is a need for a means to reassemble incoming ATM cells into PDUs and to pack the PDUs with status such that host memory saved.
It can also be seen that there is a need to reduce the host memory write operations for efficient use of system resources.